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| mp8761 high efficiency, 8a, 18v, synchronous, step-down converter mp8761 rev. 1.1 www.monolithicpower.com 1 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. the future of analog ic technology description the mp8761 is a fully-integrated, high- frequency, synchronous, rectified, step-down, switch-mode converter. it offers a very compact solution to achieve a 8a output current over a wide input-supply range with excellent load and line regulation. the mp8761 operates at high efficiency over a wide output-current load range. the mp8761 uses constant-on-time (cot) control mode to provide fast transient response and ease loop stabilization. an external resistor programs the operating frequency from 200khz to 1mhz. the frequency stays nearly constant as the input supply varies with the feed-forward compensation. the default under voltage lockout threshold is 4.1v, but a resistor network on the enable pin can increase this threshold. the soft start pin controls the output voltage startup ramp. an open drain power good signal indicates that the output is within nominal voltage range. it has full integrated protection features that include over-current prot ection, over-voltage protection and thermal shutdown. the mp8761 is available in a 3mm4mm qfn package, and requires a minimal number of readily-available components. features ? 2.5v to 5v operating input range with external 5v bias ? 4.5v to 18v operating input range with internal bias ? 8a output current ? low r ds(on) internal power mosfets ? proprietary switching-loss-reduction technique ? adaptive cot for ultrafast transient response ? 1.5% reference voltage over junction temperature range ( ? 40c to +125c) ? programmable soft-start time ? pre-bias start-up ? programmable switching frequency from 200khz to 1mhz ? non-latch ocp, ovp, and thermal shutdown ? output adjustable from 0.611v to 13v applications ? set-top boxes ? xdsl modem/dslam ? small-cell base stations ? personal video recorders ? flat-panel televisions and monitors ? distributed power systems all mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps website under products, quality assurance page. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application in freq vcc en pgnd bst fb sw mp8761 v in on/off c1 r fre q c5 c3 l1 r4 c4 r1 r2 c2 r3 pg agnd ss v out c6 0.01 0.1 1 10 30 40 50 60 70 80 90 100
mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 2 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. ordering information part number package top marking MP8761GL * 13-pin qfn(34mm) mp8761 MP8761GLe ** 16-pin qfn(34mm) mp8761e * for tape & reel, add suffix ?z (e.g. MP8761GL?z) ** for tape & reel, add suffix ?z (e.g. MP8761GLe?z) note: the 16-pin qfn package is preferred and recommended for new designs package reference top view pgnd 4 in 2 bst 11 12 13 910 8 7 6 vcc pg agnd ss fb freq en pgnd sw 3 1 sw 5 top view 13-pin qfn (3x4mm) 16-pin qfn (3x4mm) absolute maxi mum ratings (1) supply voltage v in ....................................... 21v v sw ....................................... ? 0.3v to v in + 0.3v v sw (30ns).................................. ? 3v to v in + 3v v bst ...................................................... v sw + 6v enable current i en (2..................................................... 2.5ma all other pins .................................?0.3v to +6v continuous power dissipation (t a =+25) (3) qfn34 ..................................................... 2.7w junction temperature ...............................150c lead temperature ....................................260c storage temperature.............. ? 65c to +150c recommended operating conditions (4) supply voltage v in ...........................4.5v to 18v output voltage v out .....................0.611v to 13v i en .............................................................. 1ma operating junction temp. (t j ). ? 40c to +125c follow layout recommendation for best performance thermal resistance (5) ja jc qfn (34mm)......................... 46 ....... 9.... c/w notes: 1) exceeding these ratings may damage the device. 2) refer to the section ?configuring the en control?. 3) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max)=(t j (max)- t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 4) the device is not guaranteed to function outside of its operating conditions. 5) measured on jesd51-7, 4-layer pcb. mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 3 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. electrical characteristics v in = 12v, t j = +25c, unless otherwise noted. parameters symbol condition min typ max units supply current supply current (shutdown) i in v en = 0v 0 1 a supply current (quiescent) i in v en = 2v, v fb = 1v 760 860 960 a mosfet high-side switch-on resistance hs rds-on t j =25c 28 m ? low-side switch-on resistance ls rds-on t j =25c 16 m ? switch leakage sw lkg v en = 0v, v sw = 0v or 12v 0 1 a current limit low-side valley current limit (6) i limit_valley 8 10 12 a low-side negative current limit (6) i limit_negative -4 -2.5 -1 a timer one-shot on time on r freq =453k ? , v out =1.2v 250 ns minimum on time (6) on_min 30 ns minimum off time (6) off_min 360 ns over-voltage and under-voltage protection ovp non-latch threshold v ovp_non- latch 117% 120% 123% v fb ovp delay ovp 2 s uvp threshold (6) v uvp 50% v fb reference and soft-start t j = -40c to +125c (7) 602 611 620 reference voltage v ref t j = +25c 605 611 617 mv feedback current i fb v fb = 650mv 50 100 na soft-start charging current i ss v ss =0v 16 20 25 a enable and uvlo enable input high voltage vih en 1.1 1.3 1.5 v enable hysteresis v en-hys 250 mv v en = 2v 5 enable input current i en v en = 0v 0 a mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 4 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. electrical characteristics (continued) v in = 12v, t j = +25c, unless otherwise noted. parameters symbol condition min typ max units vcc regulator vcc under-voltage lockout threshold rising vcc vth 3.75 3.9 4.05 v vcc under-voltage lockout threshold hysteresis vcc hys 500 mv vcc regulator v cc 4.65 4.8 4.95 v vcc load regulation icc=5ma 0.5 % power good power-good, rising threshold pg vth-hi 87% 91% 94% v fb power-good, falling threshold pg vth-lo 80% v fb power-good, low-to-high delay pg td 2.5 ms power good, sink current capability v pg sink 4ma 0.4 v power good, leakage current i pg_leak v pg = 3.3v 10 100 na thermal protection thermal shutdown (6) t sd 150 c thermal shutdown hysteresis (6) 25 c note: 6) guaranteed by design. 7) not production test, guar anteed by characterization mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 5 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. pin functions pin # 13-pin qfn pin# 16-pin qfn name description 1 1 en enable. digital input to turn the regul ator on or off. drive en high to turn on the regulator. drive it low to tu rn it off. connect en to in through a pull-up resistor or a resistive voltage divider for automatic startup. do not float this pin. 2 2 freq frequency set. requires a resistor connected between freq and in to set the switching frequency. the input voltage and the resistor connected to the freq pin determine the on time . the connection to the in pin provides line feed-forward and stabilizes the frequency during input voltage jitter. 3 3 fb feedback. connect to the tab of an exte rnal resistor divider from the output to gnd to set the output voltage. fb is also configured to realize over- voltage protection (ovp) by monitoring output voltage. place the resistor divider as close to fb pin as possib le. avoid using vias on the fb traces. 4 4 ss soft-start. connect an external capacitor to program the soft start time for the switch mode regulator. 5 5 agnd analog ground. the control circuit reference. 6 6 pg power good, the output is an open drain signal. require a pull-up resistor to a dc voltage to indicate high if the output voltage ex ceeds 91% of the nominal voltage. there is a delay from fb 91% to pg goes high. 7 7 vcc internal 4.8v ldo output. power the driver and control circuits. 5v external bias can disable the internal ldo. decoupling with 1f ceramic capacitor as close to the pin as possible. use x7r or x5r dielectric ceramic capacitors for their stable temperature characteristics. 8 8 bst bootstrap. require a capacitor connected between sw and bs pins to form a floating supply across the high-side switch driver. 9, 10 15, 16 sw switch output. connect to the inductor and bootstrap capacitor. the high- side switch drives the pin up to the v in voltage during pwm duty cycle?s on time. the inductor current drives t he sw pin negative during the off-time. the low-side switch?s on-resistance and the internal schottky diode clamp the negative voltage. connect using wide pcb traces 11, 12 10, 11, 12, 13 pgnd system ground. reference ground of the regulated output voltage. pcb layout requires extra care. connect using wide pcb traces. 13 9,14 in supply voltage. supplies power to the internal mosfet and regulator. the mp8761 operates from a +2.5v to +5v i nput rail with 5v external bias and a +4.5v to +18v input rail with internal bias. requires an input decoupling capacitor. connect using wide pcb traces and multiple vias. mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 6 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical characteristics vin = 12v, v out = 1v, l = 1h, t a = 25c, unless otherwise noted. mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 7 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical characteristics (continued) v in = 12v, v out = 1v, l = 1h, t a = 25c, unless otherwise noted. 4 4.2 4.4 4.6 4.8 5 -50 0 50 100 150 200 300 400 500 600 -50 0 50 100 150 100 300 500 700 900 100 300 500 700 900 0 0 5 10 15 20 25 30 35 02468 02468 600 605 610 615 620 -50 0 50 100 150 mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 8 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics v in = 12v, v out = 1v, l = 1h, t a = 25c, unless otherwise noted. mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 9 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1v, l=1h, t a =+25c, unless otherwise noted. v out 500mv/div. v in 10v/div. sw 10v/div. i l 5a/div. v out 500mv/div. v in 10v/div. sw 10v/div. i l 2a/div. v out 500mv/div. v in 5v/div. sw 10v/div. i l 5a/div. v out 500mv/div. en 5v/div. sw 10v/div. i l 2a/div. v out 500mv/div. en 5v/div. sw 10v/div. i l 5a/div. v out 500mv/div. en 5v/div. sw 10v/div. i l 2a/div. v out 500mv/div. en 5v/div. sw 10v/div. i l 5a/div. v out (ac) 500mv/div. i l 10a/div. sw 10v/div. short circuit protection v out 500mv/div. i l 2a/div. sw 10v/div. mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 10 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1v, l=1h, t a =+25c, unless otherwise noted. v out 500mv/div. i l 2a/div. sw 10v/div. thermal recovery i out = 0a mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 11 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. block diagram 0. 6v 0.3v 0.75 v figure 1: functional block diagram mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 12 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. operation pwm operation the mp8761 is a fully-integrated, synchronous, rectified, step-down, switch-mode converter. it uses constant-on-time (cot) control to provide a fast transient response and ease loop stabilization. at the beginning of each cycle, the high-side mosfet (hs-fet) turns on when the feedback voltage (v fb ) drops below the reference voltage (v ref ), which indicates an insufficient output voltage. the input voltage and the frequency-set resistor determine the on period as follows: 4 0 3 5 . ) v ( v ) k ( r . ) ns ( in freq on ? = (1) after the on period elapses, the hs-fet turns off. it turns on again when v fb drops below v ref . by repeating this operation, the converter regulates the output voltage. the integrated low- side mosfet (ls-fet) turns on when the hs- fet is off to minimize conduction loss and avoid a dead short (or shoot-through) between input and gnd if both hs-fet and ls-fet turn on at the same time. an internally-generated dead-time (dt) between hs-fet off and ls- fet on or ls-fet off and hs-fet on avoids shoot-through. heavy-load operation figure 2: heavy-load operation when the output current is high and the inductor current is always above zero amps, it is called continuous-conduction-mode (ccm). figure 2 shows the ccm operation. when v fb mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 14 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. ramp with a small esr capacitor use an external ramp when using ceramic output capacitors, because the esr ripple is not high enough to stabilize the system. r1 r2 ceramic sw fb v out l r4 c4 i r4 i c4 i fb r9 figure 7: simplified pwm-mode circuit with external ramp compensation figure 7 shows the simplified circuit in pwm mode with the hs-fet off and an external ramp compensation circuit (r4, c4). design the external ramp based on the inductor ripple current. select c4, r9, r1 and r2 to meet the following condition: ? ? ? ? ? ? + + < 9 2 1 2 1 5 1 4 2 1 r r r r r c f sw (5) where: 4 c fb 4 c 4 r i i i i + = (6) then estimate the ramp on v fb as: ? ? ? ? ? ? + ? = 9 2 1 2 1 4 4 r r // r r // r c r v v v on out in ramp (7) the v fb ripple?s descending slope is then: 4 4 1 c r v v v out off ramp slope ? = = (8) equation 8 shows that if there is instability in pwm mode, reduce either r4 or c4. if c4 is irreducible due to limitations from equation 5, then reduce r4. for stable pwm operation, design v slope1 based on equation 9. sw on 3 esr out out slope1 out out sw on tt rc i10 0.7 2 vv 2lc t t ? +? ? + ? (9) where i out is the load current. in skip mode, the v fb ripple?s descending slope is almost the same whether the external ramp is used or not. figure 8 shows the simplified circuit in skip mode when both the hs-fet and ls-fet are off. r1 r2 c out fb v out r out figure 8: simplified skip-mode circuit determine the v fb ripple?s descending slope in skip mode as follows: out out ref 2 slope c ] r // ) 2 r 1 r [( v v + ? = (10) where r out is the equivalent load resistor. figures 5 shows that v slope2 in skip mode is lower than it is in pwm mode, so it is reasonable that the jitter in skip mode is larger. to achieve less jitter during ultra-light-load conditions, reduce r1 and r2, though that will decrease the light-load efficiency. configuring the en control the regulator turns on when en goes high. conversely it turns off when en goes low. do not float the pin. for automatic start-up, pull the en pin up to the input voltage through a resistive voltage divider. choose the values of the pull-up resistor (r up , from the in pin to the en pin) and the pull-down resistor (r down , from the en pin to gnd) to determine the automatic start-up voltage: up down in start down (r r ) v1.3 (v) r ? + = (11) for example, for r up =100k ? and r down =20k ? , the v in-start is set at 7.8v. to reduce noise, add a 10nf ceramic capacitor from en to gnd. an internal zener diode on the en pin clamps the en pin voltage to prevent runaway. the maximum pull-up current (assuming the worst mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 15 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. case, 6v) for the internal zener clamp should be less than 1ma. therefore, when driving en with an external logic signal, use an en voltage less than 6v; when connecting en to in through a pull-up resistor or a resistive voltage divider, select a resistance that ensures a maximum pull up current less than 1ma. if using a resistive voltage divider and v in exceeds 6v, then the minimum resistance for the pull-up resistor r up should meet: in up down v6v 6v 1m a rr ? ? (12) with only r up (the pull-down resistor r down is not connected), then the vcc uvlo threshold determines v in-start so the minimum resistor value is: in up v6v r() 1m a ? ? (13) a typical pull-up resistor is 100k ? . soft-start the mp8761 employs soft-start (ss) to ensure a smooth output during power-up. when the en pin goes high, an internal current source (20 a) charges the ss capacitor. the ss capacitor voltage takes over the ref voltage to the pwm comparator. the output voltage smoothly ramps up with the ss voltage. it continues ramping up while v ref takes over the pwm comparator. at this point, soft-start finishes and the device enters steady state operation. determine the ss capacitor value as follows: () () () () = ss ss ss ref tmsi a cnf vv (14) if the output capacitors are large, then avoid setting a short ss time or risk hitting the current limit during ss. use a minimum value of 4.7nf if the output capacitance value exceeds 330 f. pre-bias startup the mp8761 is designed for monotonic startup for pre-biased loads. if the output is pre-biased to a certain voltage during startup, the ic will disable switching for both high-side and low-side switches until the voltage on the soft-start capacitor exceeds the sensed output voltage at the fb pin. power good (pg) the mp8761 has a power-good (pg) output. the pg pin is the open drain of a mosfet. connect it to vcc or some other voltage source that measures less than 5.5v through a pull-up resistor (typically 100k ? ). after applying the input voltage, the mosfet turns on so that the pg pin is pulled to gnd before the ss is ready. after the fb voltage reaches 91% of the ref voltage, the pg pin is pulled high after a 2.5ms delay. when the fb voltage drops to 80% of the ref voltage or exceeds 120% of the nominal ref voltage, the pg pin is pulled low. if the input supply fails to power the mp8761, the pg pin is also pulled low even though this pin is tied to an external dc source through a pull-up resistor (typically. 100k ? ). over-current protection (ocp) the mp8761 features two current limit levels for over-current conditions: low-side valley current limit and low-side negative current limit. low-side valley current limit: the device monitors the inductor current during ls-fet on state. at the end of off time, the ls-fet sourcing current is compared to the internal positive-valley-current limit. if the valley current limit is less than ls-fet sourcing current, the ls-fet turns off and the hs- fet turns on for a fixed time determined by frequency-set resistor r freq and input voltage. during ocp, the device tries to recover from the over-current fault with hiccup mode: the chip disables the output power stage, discharges the soft-start capacitor and then automatically retries soft-start. if the over- current condition still holds after soft-start ends, the device repeats this operation cycle until the over-current conditions disappear and then output rises back to regulation level. ocp offers non-latch protection. low-side negative current limit: if the sensed ls-fet negative current exceeds the mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 16 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. negative current limit, the ls-fet turns off immediately and stays off for the reminder for the off period. in this situation, both mosfets are off until the end of a fixed interval. the hs-fet body diode conducts the inductor current for the fixed time. over-voltage protection (ovp) the mp8761 monitors the output voltage using the fb pin connected to the tap of a resistor divider. if the fb voltage exceeds the nominal ref voltage but remains below 120% of the ref voltage (0.611v), both mosfets are off. if the fb voltage exceeds 120% of the ref voltage but remains below 130%, the ls-fet turns on while the hs-fet remains off. the ls-fet remains on until the fb voltage drops below 110% of the ref voltage or the low-side negative current limit triggers. if the fb voltage exceeds 130% of the ref voltage, the device enters a non-latch off mode. once the fb voltage rises to a reasonable value, it will exit ovp and operate normally. uvlo protection the mp8761 has under-voltage lockout (uvlo). when the vcc voltage exceeds the uvlo-rising threshold, the mp8761 powers up. it shuts off when the vcc voltage falls below the uvlo falling threshold. this is non-latch protection. the mp8761 is disabled when the vcc voltage falls below 3.4v. if an application requires a higher uvlo threshold, use the two external resistors connected to the en pin as shown in figure 9 to adjust the startup input voltage. for best results, use the enable resistors to set the input voltage falling threshold (v stop ) above 4 v. set the rising threshold (v start ) to provide enough hysteresis to account for any input supply variations. en comparator r up r down in en figure 9: adjustable uvlo thermal shutdown the mp8761 has thermal shutdown. the ic internally monitors the junction temperature. if the junction temperature exceeds the threshold value (minimum 150c), the converter shuts off. this is a non-latch protection. there is ~25c hysteresis. once the junction temperature drops to ~125c, it initiates a soft-start. mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 17 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. application information output-voltage, large-esr capacitors for applications that use electrolytic or pos capacitors with large esr values as output capacitors, the feedback resistors?r1 and r2 as shown in figure 10?set the output voltage. r1 r2 esr poscap sw v out l fb figure 10: simplified poscap circuit first, choose an r2 that balances between high quiescent current loss (lower r2) and high noise sensitive on fb (higher r2). a typical value falls within 5k ? -50k ? , using a comparatively larger r2 when v out is low, and a smaller r2 when v out is high. then calculate r1 as follows: out out ref ref 1 vvv 2 r1 r2 v ? ? = (15) where out v is the output ripple determined by equation 24. output-voltage, small-esr capacitors r1 r2 ceramic sw fb v out l r9 r4 c4 figure 11: simplified ceramic capacitor circuit when using a low-esr, ceramic capacitor on the output, add an external voltage ramp to the fb pin (r4 and c4). the ramp voltage (v ramp ) and the resistor divider (shown in figure 11) influence the output voltage . calculate v ramp as shown in equation 7. select r2 to balance between high quiescent current loss and fb noise sensitivity. choose r2 within 5k ? -50k ? , using a larger r2 when v out is low, and a smaller r2 when v out is high. determine the value of r1 as follows: 9 r 4 r 2 r v v v 2 r 1 r ) avg ( fb out ) avg ( fb + ? ? = (16) where v fb(avg) is the average fb voltage. v fb(avg) varies with the v in , v out , and load condition, where the load regulation is strictly related to the v fb(avg) . also the line regulation is related to the v fb(avg) ?improving load or line regulation involves a lower v ramp that meets equation 9. for pwm, estimate v fb(avg) from equation 17. 9 r 2 r // 1 r 2 r // 1 r v 2 1 v v ramp ref ) avg ( fb + + = (17) usually, r9 is 0 ? , though it can also be set following equation 18 for better noise immunity. it should also be less than 20% of r1//r2 to minimize its influence on v ramp . 1r1r2 r9 5r1r2 < + (18) using equations 16 and 17 to calculate the output voltage can be complicated. to simplify the r1 calculation in equation 16, add a dc- blocking capacitor (c dc ) to filter the dc influence from r4 and r9. figure 12 shows a simplified circuit with external ramp compensation and a dc-blocking capacitor. the addition of this capacitor simplifies the r1 calculation as per equation 19 for pwm mode operation. 2 r v 2 1 v v 2 1 v v 1 r ramp ref ramp ref out + ? ? = (19) for best results, select a c dc value at least 10c4 for better dc blocking performance, but smaller than 0.47uf to account for start-up performance. to use a larger c dc for better fb noise immunity, reduce r1 and r2 to limit their effects on system start-up. note that even with c dc , the load and line regulation are still related to v ramp . mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 18 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. r1 r2 ceramic sw fb v out l c dc r4 c4 figure 12: simplified ceramic capacitor circuit with dc-blocking capacitor input capacitor the input current to the step-down converter is discontinuous, and therefore, requires a capacitor to supply the ac current to the step- down converter while maintaining the dc-input voltage. use ceramic capacitors for best performance. during layout, place the input capacitors as close to the in pin as possible. the capacitance can vary significantly with temperature. use capacitors with x5r and x7r ceramic dielectrics because they are fairly stable over a wide temperature range. the capacitors must also have a ripple-current rating that exceeds the converter?s maximum input ripple current. estimate the input ripple current as follows: ) v v 1 ( v v i i in out in out out cin ? = (20) the worst-case condition occurs at v in = 2v out , where: 2 i i out cin = (21) for simplification, choose an input capacitor with an rms current rating that exceeds half the maximum load current. the input capacitance value determines the converter input voltage ripple. select a capacitor value that meets the input voltage ripple requirement estimate the input voltage ripple as follows: ) v v ( v v c f i v in out in out in sw out in ? = 1 (22) the worst-case condition occurs at v in = 2v out , where: in sw out in c f i v = 4 1 (23) output capacitor the output capacitor maintains the dc output voltage. use ceramic capacitors or poscaps estimate the output voltage ripple as: ) c f r ( ) v v ( l f v v out sw esr in out sw out out + ? = 8 1 1 (24) when using ceramic capacitors, the capacitance dominates the impendence at the switching frequency. the capacitance also dominates the output voltage ripple. for simplification, estimate the output voltage ripple as: ) v v ( c l f v v in out out sw out out ? = 1 8 2 (25) the esr contributes minimally to the output voltage ripple, thus requiring an external ramp to stabilize the system. design the external ramp with r4 and c4 as per equations 5, 8, and 9. the esr dominates the switching-frequency impedance for poscaps. the esr ramp voltage is high enough to stabilize the system thus eliminating the need for an external ramp. select a minimum esr value of ~12m ? to ensure stable operation. for simplification, the output ripple can be approximated as: esr in out sw out out r ) v v ( l f v v ? = 1 (26) inductor the inductor supplies constant current to the output load while being driven by the switching input voltage. a larger value inductor results in less ripple current and lower output ripple voltage, but is physically larger, has a higher series resistance, and often a lower saturation current. generally, select an inductor value that allows the inductor peak-to-peak ripple current that is 30% to 40% of the maximum switch current limit. also, design for a peak inductor current that is mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 19 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. below the maximum switch-current limit. calculate the inductance value as: ) v v ( i f v l in out l sw out ? = 1 (27) where i l is the peak-to-peak inductor ripple current. choose an inductor that will not saturate under the maximum inductor peak current. the peak inductor current can be calculated as: ) v v ( l f v i i in out sw out out lp ? + = 1 2 (28) table 1 lists a few highly-recommended high- efficiency inductors. table 1: inductor selection guide part number manufacturer inductance (h) dcr (m ? ) current rating (a) dimensions l w h (mm 3 ) switching frequency (khz) 744325072 wurth 0.72 1.35 35 10.2 10.5 4.7 500 744325180 wurth 1.8 3.5 18 10.2 10.5 4.7 500 fda1055-2r2m toko 2.2 3. 94 20.6 11.6 10.8 5.5 500 typical design parameters tables 2 and 3 list recommended component values for typical output voltages (1v, 2.5v, 3.3v) and switching frequency (500khz). refer to table 2 for design cases without external ramp compensation and table 3 for design cases with external ramp compensation. an external ramp is not needed when using high-esr capacitors, such as electrolytics or poscaps. use an external ramp when using low-esr capacitors, such as ceramic capacitors. for cases not listed in this datasheet, conctact a local sales representative for an excel spreadsheet to assist with the calculation. table2: f sw =500khz, v in =12v v out (v) l ( h) r1 (k ? ) r2 (k ? ) r freq (k ? ) 1 0.72 13.3 20 357 2.5 1.8 63.4 20 887 3.3 2.2 91 20 1200 table 3: f sw =500khz, v in =12v v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r freq (k ? ) 1 0.72 13.7 20 750 220 357 2.5 1.8 66.5 20 1000 220 887 3.3 2.2 95.3 20 1200 220 1200 mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 20 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. layout recommendations 1. mps offers two packages, but recommends MP8761GLe with its 16-pin qfn package for all new designs due to its smaller parasitical inductance. 2. place high current paths (gnd, in, and sw) very close to the device with short, direct and wide traces. 3. the 13-pin qfn package requires two copper in layers for better performance. respectively put at least one decoupling capacitor on both top and bottom layers and as close to the in and gnd pins as possible. add several vias with 18mil and 8mil hole diameters under the device and near the input capacitors to help dissipate heat and to reduce parasitic inductances. 4. place a decoupling capacitor as close to the vcc and agnd pins as possible. 5. keep the switching node (sw) plane as small as possible and far away from the feedback network. 6. place the external feedback resistors next to the fb pin. make sure that there are no vias on the fb trace. the feedback resistors should refer to agnd instead of pgnd. 7. keep the bst voltage path (bst, c3, and sw) as short as possible. 8. mps strongly recommends a four-layer layout to improve thermal performance. figure 13: schematic reference for pcb layout in r3 r1 r3 r2 r3 r4 r3 c4 r3 c6 l1 r3 c2 vin gnd sw vout en freq fb ss agnd pg vcc bs t pgn d pgn d sw sw r3 c1a r3 r5 r3 c3 r3 c5 r3 r3 gnd r3 r freq r3 c1b top layer gnd inner1 layer gnd inner2 layer mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 21 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. r3 c1c vin gnd figure 14: bottom layer, 13-pin pfn mp8761 pcb layout guide pgnd pg n d in sw pgnd pgnd in sw b s t v c c p g a g n d s s f b f r e q e n c1d top layer inner1 layer inner2 layer bottom layer figure 15?pcb layout guide for MP8761GLe (16-pin qfn) design example table 8 lists the specifications for a design example that follows the application guidelines: table 8: design example v in 12v v out 1v f sw 500khz the detailed application schematic is shown in figure 16. the typical performance and circuit waveforms have been shown in the typical performance characteristics section. for more device applications, please refer to the related evaluation board datasheet. mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 22 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical application in freq vcc en pgnd bst fb sw mp 8761 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0. 1uf c1d 0.1uf 357k r5 100k 1uf 100k r3 4.7 1uh 750 k 220pf 13.7k 20k r9 100 v out c2 a 47uf c2 b 47uf c2 c 47 uf c2d 0. 1uf 0. 1uf c2e 0.1 uf figure 16?typical application circuit with low esr ceramic capacitor for 1v output mp8761 ? 8a, 18v, synchronou s step-down converter mp8761 rev. 1.1 www.monolithicpower.com 23 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. package information 13-pin qfn (34mm) side view bottom view note: 1) all dimensions are in millimeters. 2) exposed paddle size does not include mold flash. 3) lead coplanarity shall be 0.10 millimeters max. 4) jedec reference is mo-220. 5) drawing is not to scale. top view recommended land pattern pin 1 id marking pin 1 id index area pin 1 id 0 .125 x45 ? yp. 0.125 x45 mp8761 ? 8a, 18v, synchronou s step-down converter notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. mp8761 rev. 1.1 www.monolithicpower.com 24 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. package information 16-pin qfn (34mm) side view bottom view note: 1) all dimensions are in millimeters . 2) exposed paddle size does not include mold flash. 3) lead coplanarity shall be 0.10 millimeters max. 4) jedec reference is mo -220. 5) drawing is not to scale . top view recommended land pattern pin 1 id marking pin 1 id index area pin 1 id 0.125x45 typ. 0. 125x45 |
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